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features ? drives two ultrasound tran sducer channels ? generates 5-level waveform ? drives 12 high voltage mosfets ? 2.0a source and sink peak current ? up to 20mhz output frequency ? 12v/ns slew rate ? 3ns matched delay times ? second harmonic is less than -40db ? two separate gate drive voltages ? 1.8 to 3.3v cmos logic interface applications ? medical ultrasound imaging ? piezoelectric transducer drivers ? non-destructive testing (ndt) ? metal faw detection ? sonar transmitter general description the su pertex md1711 is an ic for a two-channel, 5-level, high voltage and high speed transmitter driver. it is designed for medical ultrasound imaging applications, but can also be used for metal faw detection, non-destructive testing (ndt), and for driving piezoelectric transducers. the md1711 is a two-channel logic controller circuit with low impedance mosfet gate drivers. there are two sets of control logic inputs, one for channel a and one for channel b. each channel consists of three pairs of mosfet gate drivers. these drivers are designed to match the drive requirements of the supertex tc6320. the md1711 drives six tc6320s. each pair consists of an n-channel and a p-channel mosfet. they are designed to have the same impedance and can provide peak currents of over 2.0amps. typical application circuit high speed, integrated ultrasound driver ic v nn 1 tc6320 +100v -100v +50v -50v 0v 0v 30 32 34 44 39 41 37 dv dd 2 v ss dvss -10v dvdd1 dvdd2 16 19 21 +10v vll +3.3v a vss 48 14 15 a vss sel posa / pos1a en dgnd agnd 0 md171 1 (1/2 of i/o) sub 7 18 a vss 33 36 28 25 31 dgnd 35 40 42 43 dvss 45 fb av dd1 6 0 46 47 13 1 2 3 4 5 outpa 1 outna1 outp a2 outna2 outp a3 outna3 dgnd dgnd +5.0v dvdd 1 +10v dvdd2 +5.0v +10v +10v 26 dgnd +10v -10v -10v dvdd2 dvdd1 dvdd1 tr ansduc e r 0.22f control logic & level t ranslator nega / neg1a hven1a / pos2a hven2a / neg2a clampa 0.1f 0.1f 0.1f 0.22f 0.22f 0.22f 0.22f 0.22f 0.1f 10nf 10nf 10nf 10nf 1f 1f 1f 1f v nn 2 v pp 2 v pp 1 dv dd 2 dv dd 1 dv dd 1 dv dd 1 dvdd2 dvdd1 supertex inc. supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
2 absolute maximum ratings parameter value v ll logic supply voltage -0.5v to +5.5v av dd 1, dv dd 1, positive gate drive supply -0.5v to +15v dv dd 2, positive gate drive supply -0.5v to +15v av ss , dv ss , negative gate drive supply -15v to +0.5v operating temperature range 0c to +125c storage temperature range -65c to +150c power dissipation 1.2w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin confguration package marking 48-lead lqfp 48-lead lqfp (top view) 1 48 yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking yyww md1711f g lllllllll cccccccc aaa 48-lead qfn (top view) l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = ?green? packagin g md1711k6 lllllllll yyww aaa ccc 48-lead qfn 1 48 operating supply voltages and currents (over operating conditions unless otherwise specifed, av dd 1 = dv dd 1 = dv dd 2 = 10v, av ss = dv ss = -10v, v ll = 3.3v, t a = 25c) sym parameter min typ max units conditions v ll logic supply +1.8 +3.3 +5.0 v --- av dd1 positive drive bias supply +8.0 +10.0 +12.6 v --- dv dd1 positive gate drive supply +4.75 - +12.60 v --- dv dd2 positive gate drive supply +4.75 - +12.60 v --- av ss, dv ss negative gate drive and bias supply -12.0 -10.0 -8.0 v --- i vll logic supply current - 2.0 - ma all channels on at 5.0mhz, no load i avdd1 positive bias current - 5.0 - i avss & i dvss negative drive and bias supply current - 20 - i dvdd1 positive drive current 1 - 55 - i dvdd2 positive drive current 2 - 13 - ma all channels on at 5.0mhz, d vdd 2 = 5.0, no load package may or may not include the following marks: si or package may or may not include the following marks: si or -g denotes a lead (pb)-free / rohs compliant package part number package options packing md1711fg-g 48-lead lqfp 250/tray md1711fg-g m931 48-lead lqfp 3000/reel md1711k6-g 48-lead (7x7mm) qfn 250/tray md1711k6-g m933 48-lead (7x7mm) qfn 2000/reel package ja 48-lead lqfp 52c/w 48-lead qfn 18c/w typical thermal resistance ordering information supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
3 dc electrical characteristics (over operating conditions unless otherwise specifed, av dd 1 = dv dd 1 = dv dd 2 = 10v, av ss = dv ss = -10v, v ll = 3.3v, t a = 0 to 70c) p-channel gate driver outputs r sink output sink resistance - - 6.0 i sink = 100ma r source output source resistance - - 6.0 i source = 100ma i sink peak output sink current - 2.0 - a --- i source peak output source current - 2.0 - a --- n-channel gate driver outputs r sink output sink resistance - - 10 i sink = 100ma r source output source resistance - - 10 i source = 100ma i sink peak output sink current - 1.5 - a --- i source peak output source current - 1.5 - a --- logic inputs v ih input logic high voltage 0.8v ll - v ll v --- v il input logic low voltage 0 - 0.2v ll v --- i ih input logic high current - - 1.0 a --- i il input logic low current -1.0 - - a --- ac electrical characteristics (over operating conditions unless otherwise specifed, av dd 1 = dv dd 1 = dv dd 2 = 10v, av ss = dv ss = -10v, v ll = 3.3v, t a = 0 to 70c) f out output frequency range - - 20 mhz --- t ph propagation delay when output is from low to high - 19 - ns no load, see timing diagram t pl propagation delay when output is from high to low - 19 - ns no load, see timing diagram t r output rise time - 8.0 - ns 1000pf load, see timing diagram t f output fall time - 8.0 - ns 1000pf load, see timing diagram t dm delay time matching - - 3.0 ns no load, from device to device t dlay output jitter - 30 - ps standard deviation of t d samples (1k) operating supply voltages and currents (cont.) (over operating conditions unless otherwise specifed, av dd 1 = dv dd 1 = dv dd 2 = 10v, av ss = dv ss = -10v, v ll = 3.3v, t a = 25c) sym parameter min typ max units i avdd1q v avdd 1 quiescent current - 2.0 - ma en = low, all inputs low or high. i avssq v avss quiescent current - 0.75 - ma i dvdd1q v dvdd 1 quiescent current - - 10 a i dvdd2q v dvdd 2 quiescent current - - 10 a i vllq logic supply current - 1.0 - ma supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
4 ac electrical characteristics (cont.) (over operating conditions unless otherwise specifed, av dd 1 = dv dd 1 = dv dd 2 = 10v, av ss = dv ss = -10v, v ll = 3.3v, t a = 0 to 70c) sym parameter min typ max min comments sr output slew rate - 12 - v/ns measured at tc6320 output with 100 load hd2 2 nd harmonic distortion - -40 - db power-up sequence step connection description 1 av ss , dv ss negative gate drive supply and substrate bias 2 v ll , av dd 1, dv dd 1 & dv dd 2 logic supply, positive gate drive supply and bias test circuit for channel a dv dd 2 gp a1 hvoutp a1 out -na3 r load 100 hvout a 10nf 10nf +10v av dd 1 +10v dv dd 1 +10vdv dd 2 +3.3v vll en posa/pos1a nega/neg1a hven1a/pos2a hven2a/neg2a clamp a sel agnd dgnd a vss dvss -10v +100v -100v +50v -50v 1/2 of md171 1 3x tc6320 channel a control logic and level t ranslation dv dd 2 dv dd 1 dv dd 1 dv dd 1 dv ss vpp1 vpp2 vnn1 vnn2 out -p a3 out -na2 out -p a2 out -na1 out -p a1 10nf 10nf hvoutna1 hvoutp a2 hvoutna2 hvoutp a3 hvoutna3 gna1 gp a2 gna2 gp a3 gna3 vpp3 vnn3 supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
5 truth table for channels a and b (for sel = l) logic control inputs v pp 1 to v nn 1 output v pp 2 to v nn 2 output v pp 3 to v nn 3 output sel en hven1/ pos2 hven2/ neg2 clamp pos/ pos1 neg/ neg1 hv out p1 hv out n1 hv out p2 hv out n2 hv out p3 hv out n3 0 1 0 0 0 0 0 off off on on 0 1 0 0 0 0 1 on on 0 1 0 0 0 1 0 on on 0 1 0 0 0 1 1 off off 0 1 0 0 1 0 0 off off off 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 0 0 off off off on on 0 1 0 1 0 0 1 off on off off 0 1 0 1 0 1 0 on off off off 0 1 0 1 0 1 1 off off off off 0 1 0 1 1 0 0 off off off 0 1 0 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 0 0 off off off on on 0 1 1 0 0 0 1 off on off off 0 1 1 0 0 1 0 on off off off 0 1 1 0 0 1 1 off off off off 0 1 1 0 1 0 0 off off off 0 1 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 off off off 0 1 1 1 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 0 0 off off off 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 x x x x x off off off supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
6 truth table for channels a and b (for sel = h) logic control inputs v pp 1 to v nn 1 output v pp 2 to v nn 2 output v pp 3 to v nn 3 output sel en clamp hven1/ pos2 hven2/ neg2 pos/ pos1 neg/ neg1 hv out p1 hv out n1 hv out p2 hv out n2 hv out p3 hv out n3 1 1 0 0 0 0 0 off off off off off 1 1 0 0 0 0 1 off on 1 1 0 0 0 1 0 on off 1 1 0 0 0 1 1 on on 1 1 0 0 1 0 0 off off off on off 1 1 0 0 1 0 1 off on 1 1 0 0 1 1 0 on off 1 1 0 0 1 1 1 on on 1 1 0 1 0 0 0 off off on off off 1 1 0 1 0 0 1 off on 1 1 0 1 0 1 0 on off 1 1 0 1 0 1 1 on on 1 1 0 1 1 0 0 off off on on off 1 1 0 1 1 0 1 off on 1 1 0 1 1 1 0 on off 1 1 0 1 1 1 1 on on 1 1 1 0 0 0 0 off off off off on 1 1 1 0 0 0 1 off on 1 1 1 0 0 1 0 on off 1 1 1 0 0 1 1 on on 1 1 1 0 1 0 0 off off off on on 1 1 1 0 1 0 1 off on 1 1 1 0 1 1 0 on off 1 1 1 0 1 1 1 on on 1 1 1 1 0 0 0 off off on off on 1 1 1 1 0 0 1 off on 1 1 1 1 0 1 0 on off 1 1 1 1 0 1 1 on on 1 1 1 1 1 0 0 off off on on on 1 1 1 1 1 0 1 off on 1 1 1 1 1 1 0 on off 1 1 1 1 1 1 1 on on 1 0 x x x x x off off off off off supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
7 timing diagram posa/pos1a nega/neg1a 0v v ll hven2a/neg2 a v pp 1 v nn 1 v pp 2 v nn 2 hv out a t r1 , rise time from 0.9v nn 1 to 0.9v pp 1 f ou t 0v 3.3v in t ph 10% 90% 50% 0v 10v 50% out t pl t r 90% 10% t t f1 , fall time from 0.9v pp 1 to 0.9v nn 1 t r2 , rise time from 0.9v nn 2 to 0.9v pp 2 t f2 , fall time from 0.9v pp 2 to 0.9v nn 2 v ll v ll v ll 0v 0v 0v 0v hven1a/pos2a supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
8 block diagram 10nf 10nf + 100 v 1.0f dvdd1 10nf 10nf 10nf 10nf 10nf 10nf tc 63 2 0 dvdd2 av dd1 vll sel en a vss d vss agnd dgnd posa/pos1a clamp a nega/neg1a hven1a/pos2a hven2a/neg2a posb/pos1b clamp negb/neg1b h ven1b/pos2b h ven2b/neg2 b dv dd 1 v ss p iezoelectric tr ansducer a c ontrol logic a nd l evel t ranslate md171 1 -100v 1.0f +100v 1.0f -100v 1.0f +100v 1.0f -100v 1.0f +100v 1.0f -100v 1.0f dv dd 1 dv dd 1 dv dd 2 dv dd 2 dv dd 1 dv dd 1 v ss dv dd 1 dv dd 2 dv dd 2 p iezoelectric tr ansducer b supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
9 pin description pin # name description 1 posa / pos1a logic input control for channel a. when sel = l, the pin is posa. when sel = h, the pin is pos1a. 2 nega / neg1a logic input control for channel a. when sel = l, the pin is nega. when sel = h, the pin is neg1a. 3 hven1a / pos2a logic input control for channel a. when se l= l, the pin is hven1a. when sel = h, the pin is pos2a. 4 hven2a / neg2a logic input control for channel a. when sel = l, the pin is hven2a. when sel = h, the pin is neg2a. 5 clampa used with sel = h. logic input control for out-pa3 and out-na3. connect to ground when sel = l. 6 av dd 1 supplies analog circuitry portion of the gate driver. should be at the same potential as dv dd 1. 7 agnd analog ground. 8 clampb used with sel = h. logic input control for out-pb3 and out-nb3. connect to ground when sel = l. 9 hven2b / neg2b logic input control for channel b. when sel = l, the pin is hven2b. when sel = h, the pin is neg2b. 10 hven1b / pos2b logic input control for channel b. when sel = l, the pin is hven1b. when sel = h, the pin is pos2b. 11 negb / neg1b logic input control for channel b. when sel = l, the pin is negb. when sel = h, the pin is neg1b. 12 posb / pos1b logic input control for channel b. when sel = l, the pin is posb. when sel = h, the pin is pos1b. 13 sel logic input select. see truth tables for sel = l and sel = h. 14 avss negative driver supply for out-pa3, out-pb3 and bias circuits. they are also connected to the ic substrate. they are required to connect to the most negative potential of voltage supplies. 15 16 dvss gate drive supply voltage for out-pa3 and out-pb3. supplies digital circuitry portion and the main output stage. should be at the same potential as avss. 17 out-pb3 output p-channel gate driver for channel b. 18 dgnd digital ground. 19 dv dd 1 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa2, out-na2, out-na3, out-pb2, out-nb2, and out-nb3. should be at the same potential as av dd 1. 20 out -pb2 output p-channel gate driver for channel b. 21 dv dd 2 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa1, out-na1, out-pb1, and out-nb1. can be at a different po - tential than dv dd 1. 22 out -pb1 output p-channel gate driver for channel b. 23 n/c no connect. 24 out -nb1 output n-channel gate driver for channel b. 25 dv dd 2 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa1, out-na1, out-pb1, and out-nb1. can be at a different po - tential than dv dd 1. supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
10 pin # name description 26 dgnd digital ground. 27 out -nb2 output n-channel gate driver for channel b 28 dv dd 1 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa2, out-na2, out-na3, out-pb2, out-nb2, and out-nb3. should be at the same potential as av dd 1. 29 out -nb3 output n-channel gate driver for channel b 30 dgnd digital ground. 31 dv dd 1 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa2, out-na2, out-na3, out-pb2, out-nb2, and out-nb3. should be at the same potential as av dd 1. 32 out-na3 output n-channel gate drivers for channel a. 33 dv dd 1 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa2, out-na2, out-na3, out-pb2, out-nb2, and out-nb3. should be at the same potential as av dd 1. 34 out -na2 output n-channel gate drivers for channel a. 35 dgnd digital ground. 36 dv dd 2 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa1, out-na1, out-pb1, and out-nb1. can be at a different po - tential than dv dd 1. 37 out -na1 output n-channel gate drivers for channel a. 38 n/c no connect. 39 out -pa1 output p-channel gate drivers for channel a 40 dv dd 2 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa1, out-na1, out-pb1, and out-nb1. can be at a different po - tential than dv dd 1. 41 out -pa2 output p-channel gate drivers for channel a 42 dv dd 1 gate drive supply voltage. supplies digital circuitry portion of the gate driver and the main output stage for out-pa2, out-na2, out-na3, out-pb2, out-nb2, and out-nb3. should be at the same potential as av dd 1. 43 dgnd digital ground. 44 out -pa3 output p-channel gate drivers for channel a 45 dvss gate drive supply voltage for out-pa3 and out-pb3. supplies digital circuitry portion and the main output stage. should be at the same potential as avss. 46 vll logic supply voltage. 47 en logic input enable control. when en = l, all p-channel output drivers are high and all n- channel output drivers are low. 48 avss negative driver supply for out-pa3, out-pb3 and bias circuits. they are also connected to the ic substrate. they are required to connect to the most negative potential of voltage supplies. center pad avss for the qfn package, the center pad is at avss potential. it should be externally connected to avss. supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
11 48-lead lqfp package outline (fg) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5 o max 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7 o jedec registration ms-026, variation bbc, issue d, jan. 2001. * this dimension is not specifed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-48lqfpfg version, d041309. 1 seating plane gauge plane l l1 l2 vi ew b view b seating plane top view side view note 1 (index area d1/4 x e1/4) 48 a2 a a1 b d d1 e e1 e note: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. supertex inc. www .supertex.com doc.# dsfp-md1711 e031714 md1711
12 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) 48-lead qfn package outline (k6) 7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 6.85* 1.25 6.85* 1.25 0.50 bsc 0.30 ? 0.00 0 o nom 0.90 0.02 0.25 7.00 - 7.00 - 0.40 ? - - max 1.00 0.05 0.30 7.15* 5.45 7.15* 5.45 0.50 ? 0.15 14 o jedec registration mo-220, variation vkkd-6, issue k, june 2006. * this dimension is not specifed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings are not to scale. supertex doc.#: dspd-48qfnk67x7p050, version c041009. notes: 1. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. seating plane t op vi ew side v iew bottom v iew d e d2 e2 l l1 v iew b vi ew b 1 note 3 note 2 48 1 48 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) e b a a1 a3 supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www .supertex.com) ?2014 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com md1711 doc.# dsfp-md1711 e031714

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